July 2001
E. Pedretti

Picnic Camera Complex Programmable Logic Device Implementation
--------------------------------------------------------------

This short document describes the capabilities and status of the
current Picnic VHDL circuit description code. Two separate modes of
operations are required for the Picnic camera, so two separate
circuits were designed.

1. Mode quadrant
   -------------

This mode reads a whole quadrant from the Picnic array; the image is
stored in the static ram on the Tecnobox card which is shared between
the PPC CPU and the CPLD through the PCI bus. The readout starts when
the start bit in the control Altera control register is asserted by
the CPU.  The INTA line is asserted when the readout process has
finished and a frame is present in the SRAM. During the frame readout
the following things happen:

a)	The reset line is asserted. A whole quadrant is read from the
	Picnic array (the so called reset frame, see picnic docs.) and
	stored in SRAM.

b)	The reset line is not asserted. The last quadrant readout is
	subtracted from the reset frame previously stored and stored again
	on SRAM.

1.1. Readout Parameters

Some readout parameters can be changed by the application running on
the CPU, accessing the registers on altera:

a)	Picnic clocks minimum period.

b)	Delay between picnic clock and sample assertion.

c)	Integration time.

d)	Subquadrant corner position

1.2. Things to do

a)	The circuit should be modified to allow positioning a subquadrant of
	arbitrary size in an arbitrary position, as implemented in previous
	versions of the circuit.  

b)	See section 2.2.a

2. Mode Scan
   ---------

This mode reads a limited number of pixels of arbitrary coordinates on
the camera. For better clocking efficiency the pixels should be close
and, possibly, on the same line. The pixel's voltage is read
sequentially and stored in SRAM. INTA is asserted every cycle. This
simple cycle is performed several times and stored in memory as a time
sequence. When one sequence (or scan) is finished a flag is asserted
in the control register.  The sequence is executed in this way:

a)	When the start flag in the control register is not asserted,
	Altera resets the whole picnic frame continuously.

b)	When start is asserted and the reset frame finished, the specified
	pixels are read n times according to the value specified in the
	sample_number register. Inside this cycle other fuctions might
	be specified: if the nreads register has a value larger than
	one it will read each single pixel nreads times integrating
	the value of the readouts. If nloops is greater then one the
	whole readout process will be repeated nloops times and the
	values intergrated separately for each pixel.

c)	The scan data is differentiated in the circuit and finally stored
	in SRAM

2.1 Readout parameters

Even more readout parameters can be changed in this readout mode

a)	Same as previous mode.

b)	Same as previous mode.

c)	Nloops: read the specified pixels in a loop several nloops times
	and integrates the values separately.

d)	Nreads: read the specified pixel nreads times and integrates the
	values for that pixel.

e)	Readout sequence: vector specifying the readout sequence order and
	pixel's positions.

f)	Nsamples: number of npixels sample aquired and stored to memory.


2.2 Things to do

a)	Found possible problem in camera hardware: the voltage regulators
	used on the ADC card seems to oscillate when the ADC is in
	conversion mode. The problem is noticed as spikes superposed on
	the Gaussian noise. A similar problem was noticed on the Nicmos
	camera, but at lower frequency. These problems are also visible
	in quadrant mode.

b)	The readout circuit works well for 3 pixels but is still buggy for
	6. (problem understood and will be fixed in the next release).