July 31, 1997 rev. Oct. 12, 1999 rev. Aug. 09, 2000 IOTA NICMOS3 CAMERA SUMMARY OF BOARDS MODIFICATIONS =============================== These are errors discovered with the first IOTA/NICMOS3 system, they need to be taken into account if we are going to use the spare pc boards for a future camera; and they should be taken into consideration when re-designing the pc boards for future systems. Note: All the original PC boards have the extension R1 in their part numbers. The revised ones, in which some of the layout errors were corrected have the extension R2. Note: The photocopies of the PCB photoplots (for example included in the Reference Book) are annotated and indicate the layout errors found. (1) BIAS BOARD ************** (a) Eliminated R16, R 17 (see Notebook II p.99). Must put jumper wires on spare boards. This change is reflected in updated schematic (dated 98/09/19). (2) INTERFACE BOARD ******************* (a) Need to connect VDD pad to power plane. (b) Need to connect pins (17,19,21,23,25,26,28,30,32,34) of 50 pin connector to ground plane (DGND). (c) Need to fix the pin 1 labels of connectors DC37 and DB25; in order to agree with schematics they need to be both male. (d) Should add decoupling caps to 541s. (e) D10 test point is labelled D19. (*) 98/12/11: Received 3 new PCBs with changes (a,b,c). Part#: 1.006.R2 (3) ADC BOARD ************* (a) Changed R38 to 2 ohms (see Notebook I p.123). This change is reflected in updated schematic (dated 98/08/26). (b) Pin 3 of oscillator (U4) disconnected from BUSY of ADC. The purpose of that connection was to turn-off the CLOCK during AD conversions, but it was found that it takes too long for the CLOCK to turn back on, so we gave up on using this feature (see Notebook I pp. 131-132 and pp. 145-146). note: U4(3) was left floating, but specs recommend to tie it HIGH when not used. Should connect it to +5V, through 10K resistor. (c) R10 eliminated (NO jumper wire). This change is reflected in updated schematics (dated 98/08/26). (d) In future boards, should correct the PC layout error at R17 & U4(8) (see annotated PCB photolot. there should be no direct connection to power plane). (e) T.C. made an on-the-fly mod to ADC: ADC pin 9 - R=100 Ohm - C=0.01 uF - ADC pin11 (C value is uncertain, it says JCK, 103, KP5 on it) need to update schematics this mod was never incorporated in PCBs note: Apparently DM74LS21-ND is an obsolete component (AND gates). In future designs and layouts we should replace with a newer part, possibly also taking into account the fact that the logic no longer requires turning off the CLOCK during conversions (see (b) above). (*) 98/12/11: Received 3 new pc boards with changes (d). Part#: 1.004.R2 (4) SUPPLY & CLOCK DRIVER BOARD ******************************* (a) Cut 0.1" in width and length of pcb (see Notebook II p.3). (b) Put oops wire from a17-a22 to DGND on EURODIN connector (see Notebook II p.9). Correct layout on future boards. (*) 98/12/11: Received 3 new pc boards with changes (a,b). Part#: 1.005.R2 (5) BACKPLANE ************* (a) Reminder: AGND for detector card connects as explained in Notebook II p.20, and reflected in schematics and pin assignment list. (b) Connected a32=+5V -> a29, a31=DGND -> a30 of spare slot (for detector card digital power wires). (6) FILTER CARD *************** (a) Made a cut through the GND plane to separate analog and digital planes. See Notebook II p.23 for where to cut. (*) note: We have new filter boards for PICNIC design. Do not need to use NICMOS3 spares. (7) DETECTOR BOARD ****************** (a) Eliminated C16 => must short with wire on spares (connect DETSUB to AGND). This change is reflected in updated schematics (dated 98/09/19). (b) Same with R6. (c) Added 100K resistors to ground at NICMOS3/MIRROR pins (see Notebook II p.90). LOAD pins were left OPEN. This change is reflected in updated schematics (dated 98/09/19). (d) Eliminated inductor on DRAIN connection (see Notebook III p.10), on spares must short with wire. This change is reflected in updated schematics (dated 98/09/19). (*) note: We have new detector PCBs for PICNIC chip in which changes (a,b,d) were incorporated. (8) AMPLIFIER BOARD ******************* (a) Version I (T.C.): VB2 is used for cancellation of signal offset (see Notebook II p.75) (see updated schematic, dated 98/08/19). (b) Version II (P.H.): VB3 is used for signal offset. VB2 is unused. (see Notebook III p.11) (see schematic dated 97/11/08). (c) Must connect heavy wires from DB25 on AMP board grounded pins to dewar chassis, at same place that detector card ground connects to dewar chassis. note: The original amp design (version I, by Ta Chun Li) was dropped in favor of version II (by Paul Horowitz) for noise considerations based on the specs of the components used. However, an experimental comparison of the noise performance of each design was never done. (*) note: Originally, version II was used on version I PCB, by cutting traces and stuff. Now we have actual version II PCBs made for PICNIC system.